M52D5121632A Datasheet - ESMT

M52D5121632A Mobile Synchronous DRAM

The M52D5121632A is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 16 bits. Synchronous design allows precise.

M52D5121632A Features

* 1.8V power supply LVCMOS compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency (2, 3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave) EMRS cycle with address All inputs are sampled at the positive going edge of the s

M52D5121632A-ESMT.pdf