M52D5123216A Datasheet - ESMT

M52D5123216A Mobile Synchronous DRAM

The M52D5123216A is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 32 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burs.

M52D5123216A Features

* 1.8V power supply

* LVCMOS compatible with multiplexed address

* Four banks operation

* MRS cycle with address key programs - CAS Latency (2, 3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave)

* EMRS cycle with address

* All inputs are sampled

M52D5123216A-ESMT.pdf