M53D5121632A Datasheet - ESMT

M53D5121632A, Mobile DDR SDRAM

ESMT Mobile DDR SDRAM .
Ball Name Function A0~A12, BA0~BA1 Address inputs - Row address A0~A12 - Column address A0~A9 A10/AP : AUTO Precharge BA0~BA1 : Bank selects (4 Ba.

Features

* JEDEC Standard
* Internal pipelined double-data-rate architecture, two data access per clock cycle
* Bi-directional data strobe (DQS)
* No DLL; CLK to DQS is not synchronized.
* Differential clock inputs (CLK and CLK )
* Four bank operation
* CAS Latency : 2, 3
* Bu

M53D5121632A-ESMT.pdf