M53D2561616A

Mobile DDR SDRAM

ESMT

* JEDEC Standard

* Internal pipelined double-data-rate architecture, two data access per clock cycle

* Bi-directional data strobe (DQS)

* No DLL; CLK to DQS is not synchronized.

* Differential clock inputs (CLK and CLK )

* Four bank operation

* CAS Latency : 3

* Burst

M53D2561616A

ESMT

708.08 KB

Mobile ddr sdram.

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M53D2561616A Mobile DDR SDRAM ESMT

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