M53D256328A Datasheet - ESMT

M53D256328A, LPDDR SDRAM

ESMT LPDDR SDRAM .
Ball Name Function A0~A11, BA0~BA1 Address inputs - Row address A0~A11 - Column address A0~A8 A10/AP : AUTO Precharge BA0~BA1: Bank selects (4 Ban.

datasheet Preview Page 1 from Datasheet4u.com

M53D256328A-ESMT.pdf

M53D256328A Datasheet Preview — Preview of M53D256328A PDF

Datasheet Details

Part number:

M53D256328A

Manufacturer:

ESMT

File Size:

2.26 MB

Description:

LPDDR SDRAM

Features

* JEDEC Standard
* Internal pipelined double-data-rate architecture, two data access per clock cycle
* Bi-directional data strobe (DQS)
* No DLL; CLK to DQS is not synchronized.
* Differential clock inputs (CLK and CLK )
* Four bank operation
* CAS Latency : 3
* Burst

M53D256328A Distributors

📁 Related Datasheet

M53 M5300 M5301 M5302 M5303 M5304

📌 All Tags

M53D256328A LPDDR SDRAM ESMT

ESMT M53D256328A-like datasheet