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M53D128324A Datasheet - ESMT

M53D128324A - Mobile DDR SDRAM

M53D128324A Features

* JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) No DLL; CLK to DQS is not synchronized. Differential clock inputs (CLK and CLK ) Four bank operation CAS Latency : 2, 3 Burst Type : Sequential and Interleave Burst Lengt

M53D128324A-ESMT.pdf

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Datasheet Details

Part number:

M53D128324A

Manufacturer:

ESMT

File Size:

1.22 MB

Description:

Mobile ddr sdram.

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