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M53D128324A - Mobile DDR SDRAM

ESMT

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Datasheet Details

Part number	M53D128324A
Manufacturer	ESMT
File Size	1.22 MB
Description	Mobile DDR SDRAM
Datasheet	M53D128324A-ESMT.pdf

M53D128324A Product details

Features

JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) No DLL; CLK to DQS is not synchronized. Differential clock inputs (CLK and CLK ) Four bank operation CAS Latency : 2, 3 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8, 16 Special function support - PASR (Partial Array Self Refresh) - Internal TCSR (Temperature Compensated Self Refresh) - DS (Drive Strength) M53D128324A (2E) 1M x 32 Bit x 4 Banks Mobile.

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Published: Sep 20, 2018 |