M53D1G1664A - Mobile DDR SDRAM
Ball Name Function A0~A13, BA0~BA1 Address inputs - Row address A0~A13 - Column address A0~A9 A10/AP : AUTO Precharge BA0~BA1 : Bank selects (4 Banks) DQ0~DQ15 Data-in/Data-out RAS CAS WE VSS VDD LDQS, UDQS Row address strobe Column address strobe Write enable Ground Power Bi-directional Data
M53D1G1664A Features
* JEDEC Standard
* Internal pipelined double-data-rate architecture, two data access per clock cycle
* Bi-directional data strobe (DQS)
* No DLL; CLK to DQS is not synchronized.
* Differential clock inputs (CLK and CLK )
* Four bank operation
* CAS Latency : 2, 3
* Bu
