M53D1G1664A - Mobile DDR SDRAM

ESMT

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Datasheet Details

Part number	M53D1G1664A
Manufacturer	ESMT
File Size	1.87 MB
Description	Mobile DDR SDRAM
Datasheet	M53D1G1664A-ESMT.pdf

M53D1G1664A Product details

Description

Ball Name Function A0~A13, BA0~BA1 Address inputs - Row address A0~A13 - Column address A0~A9 A10/AP : AUTO Precharge BA0~BA1 : Bank selects (4 Banks) DQ0~DQ15 Data-in/Data-out RAS CAS WE VSS VDD LDQS, UDQS Row address strobe Column address strobe Write enable Ground Power Bi-directional Data Strobe.LDQS corresponds to the data on DQ0~DQ7; UDQS correspond to the data on DQ8~DQ15 Ball Name Function LDM, UDM DM is an input mask signal for write data.LDM corresponds to the data on DQ0~

Features

JEDEC Standard.
Internal pipelined double-data-rate architecture, two data access per clock cycle.
Bi-directional data strobe (DQS).
No DLL; CLK to DQS is not synchronized.
Differential clock inputs (CLK and CLK ).
Four bank operation.
CAS Latency : 2, 3.
Burst Type : Sequential and Interleave.
Burst Length : 2, 4, 8, 16.
Special function support - PASR (Partial Array Self Refresh) - Internal TCSR (Temperature Compensated Self Refresh) - DS (Dr.

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Published: Sep 20, 2018 |