M53D1G1664A Datasheet - ESMT

M53D1G1664A Mobile DDR SDRAM

Ball Name Function A0~A13, BA0~BA1 Address inputs - Row address A0~A13 - Column address A0~A9 A10/AP : AUTO Precharge BA0~BA1 : Bank selects (4 Banks) DQ0~DQ15 Data-in/Data-out RAS CAS WE VSS VDD LDQS, UDQS Row address strobe Column address strobe Write enable Ground Power Bi-directional Data.

M53D1G1664A Features

* JEDEC Standard

* Internal pipelined double-data-rate architecture, two data access per clock cycle

* Bi-directional data strobe (DQS)

* No DLL; CLK to DQS is not synchronized.

* Differential clock inputs (CLK and CLK )

* Four bank operation

* CAS Latency : 2, 3

* Bu

M53D1G1664A Datasheet (1.87 MB)

M53D1G1664A Datasheet Preview — Preview of M53D1G1664A PDF

Datasheet Details

Part number:

M53D1G1664A

Manufacturer:

ESMT

File Size:

1.87 MB

Description:

Mobile ddr sdram.

📁 Related Datasheet

M53D1G3232A Mobile DDR SDRAM (ESMT)

M53D128168A Mobile DDR SDRAM (ESMT)

M53D128324A Mobile DDR SDRAM (ESMT)

M53D2561616A Mobile DDR SDRAM (ESMT)

M53D256328A LPDDR SDRAM (ESMT)

M53D5121632A Mobile DDR SDRAM (ESMT)

M53D5123216A Mobile DDR SDRAM (ESMT)

M53D64164A Mobile DDR SDRAM (ESMT)

TAGS

M53D1G1664A Mobile DDR SDRAM ESMT

M53D1G1664A Distributor