EDD2508AKTA-5 - 256M bits DDR SDRAM (32M words x 8 bits DDR400)
The EDD2508AKTA-5 is a 256M bits DDR SDRAM organized as 8,388,608 words × 8 bits × 4 banks.
Read and write operations are performed at the cross points of the CK and the /CK.
This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture.
Data strobe (DQS) both for read and
EDD2508AKTA-5 Features
* Power supply: VDDQ = 2.6V ± 0.1V : VDD = 2.6V ± 0.1V
* Data rate: 400Mbps (max.)
* Double Data Rate architecture; two data transfers per clock cycle
* Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver
