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EDE5108AGBG Datasheet - Elpida Memory

EDE5108AGBG 512M bits DDR2 SDRAM

DATA SHEET 512M bits DDR2 SDRAM EDE5108AGBG (64M words × 8 bits) Specifications Density: 512M bits Organization ⎯ 16M words × 8 bits × 4 banks Package: 60-ball FBGA www.DataSheet4U.com ⎯ Lead-free (RoHS compliant) Power supply: VDD, VDDQ = 1.8V ± 0.1V Data rate: 667Mbps/533Mbps (max.) 1KB page size ⎯ Row address: A0 to A13 ⎯ Column address: A0 to A9 Four internal banks for concurrent operation Interface: SSTL_18

EDE5108AGBG Features

* Double-data-rate architecture; two data transfers per clock cycle

* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture

* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re

EDE5108AGBG Datasheet (674.27 KB)