DM74LS73A
Fairchild Semiconductor
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Dual negative-edge-triggered master-slave j-k flip-flops. This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed
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DM74LS73A - DUAL NEGATIVE-EDGE-TRIGGERED MASTER-SLAVE J-K FLIP-FLOPS
(National Semiconductor)
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54LS74 DM54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs
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54LS74 DM54LS74A DM74LS74.
DM74LS74A - Dual Positive-Edge-Triggered D Flip-Flops
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August 1986 Revised March 2000
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August 1986 Revised March 2000
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These latches are ideally suited for use as temporary sto.
DM74LS00 - Quad 2-Input NAND Gate
(Fairchild Semiconductor)
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August 1986 Revised March 2000
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This device contains four indepen.
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(National Semiconductor)
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June 1989
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DM74LS02 - Quad 2-Input NOR Gate
(Fairchild Semiconductor)
DM74LS02 Quad 2-Input NOR Gate
May 1986 Revised March 2000
DM74LS02 Quad 2-Input NOR Gate
General Description
This device contains four independent .
DM74LS02 - Quad 2-Input NOR Gates
(National Semiconductor)
54LS02 DM54LS02 DM74LS02 Quad 2-Input NOR Gates
June 1989
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This device contains f.
DM74LS03 - Quad 2-Input NAND Gates
(Fairchild Semiconductor)
DM74LS03 Quad 2-Input NAND Gates with Open-Collector Outputs
August 1986 Revised March 2000
DM74LS03 Quad 2-Input NAND Gates with Open-Collector Out.
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(National Semiconductor)
54LS03 DM54LS03 DM74LS03 Quad 2-Input NAND Gates with Open-Collector Outputs
June 1989
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