56F805 Datasheet - Freescale Semiconductor

56F805 16-bit Digital Signal Controllers

of Change Added revision history. Added this text to footnote 2 in Table 3-8: “However, the high pulse width does not have to be any particular percent of the low pulse width.” 56F805 General Description * Up to 40 MIPS at 80MHz core frequency * DSP and MCU functionality in a unifi.

56F805 Features

* 1.1.1 Processing Core

* Efficient 16-bit 56800 family processor engine with dual Harvard architecture

* As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency

* Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

* Two 36-bit accumulat

56F805 Datasheet (306.03 KB)