* SUMMARY
* Mobile DDR SDRAM clock cycle
* MODE RERISTER SET, EXTENDED MODE REGISTER SET and STATUS REGISTER READ - Keep to the JEDEC Standard regulation (Low Power DDR SDRAM) - Double data rate architecture: two data transfer per
* Mobile DDR SDRAM INTERFACE - x16 bus width: H5MS1262E
H5MS1262EFP Datasheet (1.35 MB)
H5MS1262EFP
Hynix Semiconductor
1.35 MB
128m (8mx16bit) mobile ddr sdram.
www.DataSheet4U.net
128Mbit MOBILE DDR SDRAM based on 2M x 4Bank x16 I/O
Specification of 128M (8Mx16bit) Mobile DDR SDRAM
Memory Cell Array
- Orga.
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