H5MS1262EFP Datasheet (Hynix Semiconductor) - 128M (8Mx16bit) Mobile DDR SDRAM

H5MS1262EFP, 128M (8Mx16bit) Mobile DDR SDRAM

and is subject to change without notice.

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Rev 1.1 / July.

2009 1 www.DataSheet4U.net 128Mbit MOBILE DDR SDRAM based on 2M x 4Bank x16 I/O Document Title 128Mbit (4Bank x 2M x 16bits) MOBILE DDR

H5MS1262EFP Features

* SUMMARY

* Mobile DDR SDRAM clock cycle

* MODE RERISTER SET, EXTENDED MODE REGISTER SET and STATUS REGISTER READ - Keep to the JEDEC Standard regulation (Low Power DDR SDRAM) - Double data rate architecture: two data transfer per

* Mobile DDR SDRAM INTERFACE - x16 bus width: H5MS1262E