H5MS1222EFP
description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Jun. 2008 1
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Mobile DDR SDRAM 128Mbit (4M x 32bit) H5MS1222EFP Series
Document Title
128MBit (4Bank x 1M x 32bits) MOBILE DDR SDRAM
Revision History
Revision No.
0.1 0.2 0.3 0.4 1.0
- Initial Draft
- Define IDD specification
- Correct t REFi specification
- Modify IDD values -. Modify IDD Values(p22,p23) , AC Characteristics(p.24)
History
Draft Date
Sep. 2007 Feb. 2008 May. 2008 Jun. 2008 Jun. 2008
Remark
Preliminary Preliminary Preliminary Preliminary
Rev 1.0 / Jun. 2008
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Mobile DDR SDRAM 128Mbit (4M x 32bit) H5MS1222EFP Series
FEATURES
SUMMARY
Mobile DDR SDRAM
- Double data rate architecture: two data transfer per clock cycle Mobile DDR SDRAM INTERFACE
- x32 bus width: HY5MS5B2ALFP
- Multiplexed Address (Row address and Column address) BURST LENGTH SUPPLY VOLTAGE
- 1.8V device: VDD and VDDQ =...
