* SUMMARY Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle Mobile DDR SDRAM INTERFACE - x32 bus width: HY5MS5B2ALFP - Multiplexed Address (Row address and Column address) BURST LENGTH SUPPLY VOLTAGE - 1.8V device: VDD and VDDQ = 1.7V to 1.95V MEMORY CELL ARRAY - 128M
H5MS1222EFP Datasheet (1.80 MB)
H5MS1222EFP
Hynix Semiconductor
1.80 MB
128mbit mobile ddr sdram.
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128Mbit MOBILE DDR SDRAM based on 1M x 4Bank x32 I/O
Specification of 128M (4Mx32bit) Mobile DDR SDRAM
Memory Cell Array
- Orga.
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