H5MS1222EFP Overview
Key Specifications
Package: FBGA
Key Features
- Double data rate architecture: two data transfer per clock cycle Mobile DDR SDRAM INTERFACE
- x32 bus width: HY5MS5B2ALFP
- Multiplexed Address (Row address and Column address) BURST LENGTH SUPPLY VOLTAGE
- 1.8V device: VDD and VDDQ = 1.7V to 1.95V MEMORY CELL ARRAY
- 128Mbit (x32 device) = 1M x 4Bank x 32 I/O DATA STROBE
- Data and data mask referenced to both edges of DQS LOW POWER FEATURES
- PASR (Partial Array Self Refresh)
- AUTO TCSR (Temperature Compensated Self Refresh)
- DS (Drive Strength)
- DPD (Deep Power Down): DPD is an optional feature, so please contact Hynix office for the DPD feature INPUT CLOCK
