H5MS1222EFP
Description
The Hynix H5MS1222EFP Series is 134,217,728-bit CMOS Low Power Double Data Rate Synchronous DRAM (Mobile DDR SDRAM), ideally suited for mobile applications which use the battery such as PDAs, 2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, hand-held PCs. It is organized as 4banks of 1,048,576 x32.
Key Features
- Double data rate architecture: two data transfer per clock cycle Mobile DDR SDRAM INTERFACE
- x32 bus width: HY5MS5B2ALFP
- Multiplexed Address (Row address and Column address) BURST LENGTH SUPPLY VOLTAGE
- 1.8V device: VDD and VDDQ = 1.7V to 1.95V MEMORY CELL ARRAY
- 128Mbit (x32 device) = 1M x 4Bank x 32 I/O DATA STROBE
- Data and data mask referenced to both edges of DQS LOW POWER FEATURES
- PASR (Partial Array Self Refresh)
- DS (Drive Strength)
- DPD (Deep Power Down): DPD is an optional feature, so please contact Hynix office for the DPD feature INPUT CLOCK
- Differential clock inputs (CK, CK) Data MASK
