* JEDEC standard 3.3V power supply All device pins are compatible with LVTTL interface 86TSOP-II, 90Ball FBGA with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by DQM0,1,2 and 3
HY57V283220LT Datasheet (938.60 KB)
HY57V283220LT
Hynix Semiconductor
938.60 KB
4 banks x 1m x 32bit synchronous dram.
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HY57V283220(L)T(P)/ HY5V22(L)F(P)
4 Banks x 1M x 32Bit Synchronous DRAM
Revision History
Revision No. 0.1 History Defined Prelim.
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