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HY57V283220TP Datasheet - Hynix Semiconductor

HY57V283220TP 4 Banks x 1M x 32Bit Synchronous DRAM

and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.9 / July 2004 HY57V283220(L)T(P)/ HY5V22(L)F(P) 4 Banks x 1M x 32Bit Synchronous DRAM DESCRIPTION The Hynix HY57V283220(L)T(P) .

www.DataSheet4U.com HY57V283220(L)T(P)/ HY5V22(L)F(P) 4 Banks x 1M x 32Bit Synchronous DRAM Revision History Revision No. 0.1 History Defined Preliminary Specification 1) 2) 3) 4) 5) 6) Modified FBGA Ball Configuration Typo. Changed Functional Block Diagram from A10 to A11. Changed VDD min from 3.0V to 3.135V. Changed Cap. Value from C11, 3, 5 to 4pf & C12, 3.8 to 4pf. Insert tAC2 Value. Insdrt tRAS & CLK Value. Remark 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Defined IDD Spec. Delited Preliminary. C.

HY57V283220TP Features

* JEDEC standard 3.3V power supply All device pins are compatible with LVTTL interface 86TSOP-II, 90Ball FBGA with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by DQM0,1,2 and 3

HY57V283220TP Datasheet (938.60 KB)