* Voltage: VDD, VDDQ 3.3V supply voltage All device pins are compatible with LVTTL interface 54 Pin TSOPII (Lead or Lead Free Package) All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM, LDQM
HY57V281620ELT Datasheet (120.33 KB)
HY57V281620ELT
Hynix Semiconductor
120.33 KB
Synchronous dram memory.
128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O Document Title
4Bank x 2M x 16bits Synchronous DRAM
Revision History
Revision No. 1.0 1.1 First Ve.
📁 Related Datasheet
HY57V281620ELTP Synchronous DRAM Memory 128Mbit (8M x 16bit) (Hynix Semiconductor)
HY57V281620EST Synchronous DRAM Memory 128Mbit (8M x 16bit) (Hynix Semiconductor)
HY57V281620ET Synchronous DRAM Memory 128Mbit (8M x 16bit) (Hynix Semiconductor)
HY57V281620ETP Synchronous DRAM Memory 128Mbit (8M x 16bit) (Hynix Semiconductor)
HY57V281620A 4 Banks x 2M x 16bits Synchronous DRAM (Hynix Semiconductor)
HY57V281620FLTP Synchronous DRAM Memory 128Mbit (8Mx16bit) (Hynix Semiconductor)
HY57V281620FSTP Synchronous DRAM Memory 128Mbit (8Mx16bit) (Hynix Semiconductor)
HY57V281620FTP Synchronous DRAM Memory 128Mbit (8Mx16bit) (Hynix Semiconductor)
HY57V281620HCT (HY57V281620HC(L/S)T) 4 Banks x 2M x 16-Bits SDRAM (Hynix Semiconductor)
HY57V281620HLT (HY57V281620HC(L/S)T) 4 Banks x 2M x 16-Bits SDRAM (Hynix Semiconductor)
