HY57V281620ET Datasheet PDF - Hynix Semiconductor Synchronous DRAM Memory 128Mbit (8M x 16bit) Specs

HY57V281620ET - Synchronous DRAM Memory 128Mbit (8M x 16bit)

This page provides the datasheet information for the HY57V281620ET, a member of the HY57V281620ELT Synchronous DRAM Memory 128Mbit (8M x 16bit) family.

Datasheet Summary

Description

and is subject to change without notice.

responsibility for use of circuits described.

No patent licenses are implied.

Features

Voltage: VDD, VDDQ 3.3V supply voltage.
4096 Refresh cycles / 64ms.
All device pins are compatible with LVTTL interface.
Programmable Burst Length and Burst Type.
54 Pin TSOPII (Lead or Lead Free Package) - 1, 2, 4, 8 or full page for Sequential Burst.
All inputs and outputs referenced to positive edge of system clock.
Data mask function by UDQM, LDQM.
Internal four banks operation.
Auto refresh and self refre.

Datasheet Details

Part number	HY57V281620ET
Manufacturer	Hynix Semiconductor
File Size	120.33 KB
Description	Synchronous DRAM Memory 128Mbit (8M x 16bit)
Datasheet	HY57V281620ET Datasheet
Additional preview pages of the HY57V281620ET datasheet.

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Full PDF Text Transcription

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128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O Document Title 4Bank x 2M x 16bits Synchronous DRAM Revision History Revision No. History 1.0 First Version Release 1.1 1. Corrected PIN ASSIGNMENT A12 to NC 1.2 1. Changed IDD3P and IDD3PS 3mA to 5mA 2. Added Industrial Temperature (-40oC to 85oC) 1.3 Changed tOH(Only Symbol ‘H’): 2.5ns -> 2.7ns 1.4 Add Super Low Power-> IDD6: 500uA Draft Date Dec. 2004 Jan. 2005 Feb. 2005 Apr. 2005 Aug. 2005 Remark This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.4 / Aug.

Published: Nov 14, 2018 |