* Voltage: VDD, VDDQ 3.3V supply voltage All device pins are compatible with LVTTL interface 54 Pin TSOPII (Lead Free Package) All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM, LDQM
HY57V281620FLTP Datasheet (773.35 KB)
HY57V281620FLTP
Hynix Semiconductor
773.35 KB
Synchronous dram memory 128mbit (8mx16bit).
128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O Document Title
4Bank x 2M x 16bits Synchronous DRAM
Revision History
Revision No. 0.1 1.0 1.1 Init.
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