Description
HY57V561620(L)T 4Banks x 4M x 16Bit Synchronous DRAM .
Features
* Single 3.3V ± 0.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM and LDQM Internal four banks opeApplications
* which require large memory density and high bandwidth. HY57V561620 is organized as 4 banks of 4,194,304x16. The HY57V561620T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data pHY57V561620L Distributors
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