HY57V561620CTP Datasheet - Hynix Semiconductor

HY57V561620CTP 4 Banks x 4M x 16Bit Synchronous DRAM

The HY57V561620C(L)T(P) Series is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V561620C(L)T(P) Series is organized as 4banks of 4,194,304x16. HY57V561620C(L)T(P) Series is offering fully synchronous.

HY57V561620CTP Features

* Single 3.3±0.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch (Leaded Package or Lead Free Package) All inputs and outputs referenced to positive edge of system clock Data mask function by UD

HY57V561620CTP Datasheet (251.31 KB)