HY57V56820BLT Features
* Single 3.3±0.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by DQM Internal four banks operation
HY57V56820BT_HynixSemiconductor.pdf
Datasheet Details
HY57V56820BLT, HY57V56820BT
Hynix Semiconductor
173.15 KB
4 banks x 8m x 8bit synchronous dram.
This datasheet PDF includes multiple part numbers: HY57V56820BLT, HY57V56820BT.
Please refer to the document for exact specifications by model.
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HY57V56820BLT Distributor
