HY57V56820CLT, HY57V56820CT Datasheet (Hynix Semiconductor)

HY57V56820CLT, HY57V56820CT, 4 Banks x 8M x 8Bit Synchronous DRAM

The HY57V56820C is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth.

The HY57V56820C is organized as 4banks of 8,388,608x8.

The HY57V56820C is offering fully synchronous operation referenced to a positive ed

HY57V56820CLT Features

* Single 3.3±0.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by DQM Internal four banks operation