HY5RS573225F - 256 GDDR3 SDRAM
and is subject to change without notice.
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Rev.
0.4 / Apr.
2004 1 HY5RS573225F Revision History Revision No.
0.1 0.2 0.3 0.4 www.DataSheet4U.com History Defined target spec.
Full Revis
HY5RS573225F Features
* VDD=1.8V ± 0.1V, VDDQ=1.8V ± 0.1V Single ended READ Strobe (RDQS) per byte Single ended WRITE Strobe (WDQS) per byte Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Ca
