HYMP512Uxxx Datasheet - Hynix

HYMP512Uxxx, DDR2 SDRAM Unbuffered DIMMs Based on 512M

240pin DDR2 SDRAM Unbuffered DIMMs based on 512 Mb 1st ver.This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 512Mb 1st ver.D.
and is subject to change without notice.

Features

* JEDEC standard Double Data Rate2 Synchrnous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface 4 Bank architecture Posted CAS Programmable CAS Latency 3 , 4 , 5 OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die Termination

HYMP512Uxxx_Hynix.pdf