HYMP512Uxxx Datasheet (Hynix) - DDR2 SDRAM Unbuffered DIMMs Based on 512M

HYMP512Uxxx, DDR2 SDRAM Unbuffered DIMMs Based on 512M

and is subject to change without notice.

Hynix Semiconductor does not assume any responsibility for use of circuits described.

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Rev.

1.0 / Apr.

2005 1 1240pin DDR2 SDRAM Unbuffered DIMMs SPEED GRADE & KEY PARAMETERS E3 (DDR2-400) Speed @CL3 Speed @CL4 Speed @CL5 CL-tR

HYMP512Uxxx Features

* JEDEC standard Double Data Rate2 Synchrnous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface 4 Bank architecture Posted CAS Programmable CAS Latency 3 , 4 , 5 OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die Termination