Description
ISSI's 128Mb Mobile Synchronous DRAM achieves highspeed data transfer using pipeline architecture.
Features
- Fully synchronous; all signals referenced to a
positive clock edge.
- Internal bank for hiding row access and pre-
charge.
- Programmable CAS latency: 2, 3.
- Programmable Burst Length: 1, 2, 4, 8, and Full
Page.
- Programmable Burst Sequence:.
- Sequential and Interleave.
- Auto Refresh (CBR).
- TCSR (Temperature Compensated Self Refresh).
- PASR (Partial Arrays Self Refresh): 1/16, 1/8,
1/4, 1/2, and Full.
- Dee.
