* Internal self-timed write cycle
* Individual Byte Write Control and Global Write
* Clock controlled, registered address, data and control
* Burst sequence control using MODE input
* Three chip enable option for simple depth ex- pansion and address pip
IS61LPS51218A Datasheet (0.98 MB)
IS61LPS51218A
ISSI
0.98 MB
Single cycle deselect static ram.
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A 256K x 36, 256K x 32, 512K x 18 9 Mb SYNCHRONOUS PIPELINED,.
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