* Internal self-timed write cycle
* Individual Byte Write Control and Global Write
* Clock controlled, registered address, data and control
* Linear burst sequence control using MODE input
* Three chip enable option for simple depth expansion and address pipel
IS61LPS51218D Datasheet (172.78 KB)
IS61LPS51218D
ISSI
172.78 KB
256kx32 synchronous pipelined static ram.
IS61SPS25632T/D IS61LPS25632T/D IS61SPS25636T/D IS61LPS25636T/D IS61SPS51218T/D IS61LPS51218T/D
256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS PIPELINE, .
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