IS61QDB21M36 Datasheet - ISSI

QUAD (Burst of 2) Synchronous SRAMs

IS61QDB21M36 Features

* 1M x 36 or 2M x 18.

* On-chip delay-locked loop (DLL) for wide data valid window.

* Separate read and write ports with concurrent read and write operations.

* Synchronous pipeline read with early write operation.

* Double data rate (DDR) interface for read a

IS61QDB21M36 General Description

The 36Mb IS61QDB21Mx36 and IS61QDB22Mx18 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operat.

IS61QDB21M36 Datasheet (645.61 KB)

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IS61QDB21M36

Manufacturer:

ISSI

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645.61 KB

Description:

Quad (burst of 2) synchronous srams.

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IS61QDB21M36 QUAD Burst Synchronous SRAMs ISSI

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IS61QDB21M36 Features

IS61QDB21M36 General Description

Datasheet Details

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