IS61QDB21M36C - 36Mb QUAD Synchronous SRAM
The Mb and are synchronous, high-performance CMOS static random access memory (SRAM) devices.
These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.
The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.
Refer t
IS61QDB21M36C Features
* 1Mx36 and 2Mx18 configuration available.
* On-chip Delay-Locked Loop (DLL) for wide data valid window.
* Separate independent read and write ports with concurrent read and write operations.
* Synchronous pipeline read with EARLY write operation.
* Double Data Rate (DDR) interfa
