IS61QDP2B21M18A - 18Mb QUADP (Burst 2) Synchronous SRAM

ISSI

Datasheet Details

Part number	IS61QDP2B21M18A
Manufacturer	ISSI
File Size	611.89 KB
Description	18Mb QUADP (Burst 2) Synchronous SRAM
Datasheet	IS61QDP2B21M18A-ISSI.pdf

at page 6 for each ODT option.

512Kx36 and 1Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data valid window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with EARLY write operation.
Double Data Rate (DDR) interface for read and write input ports.
2.0 Cycle read latency.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and co.

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Published: Jun 10, 2016 |