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IS61QDPB21M18A

18Mb QUADP (Burst 2) Synchronous SRAM

IS61QDPB21M18A Features

* 512Kx36 and 1Mx18 configuration available.

* On-chip Delay-Locked Loop (DLL) for wide data valid window.

* Separate independent read and write ports with concurrent read and write operations.

* Synchronous pipeline read with EARLY write operation.

* Double Data Rate (DDR) inter

IS61QDPB21M18A General Description

The and are synchronous, high- performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to t.

IS61QDPB21M18A Datasheet (600.50 KB)

Preview of IS61QDPB21M18A PDF

Datasheet Details

Part number:

IS61QDPB21M18A

Manufacturer:

ISSI

File Size:

600.50 KB

Description:

18mb quadp (burst 2) synchronous sram.

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IS61QDPB21M18A 18Mb QUADP Burst Synchronous SRAM ISSI

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