Description
IS61QDPB21M18A/A1/A2 IS61QDPB251236A/A1/A2 1Mx18, 512Kx36 18Mb QUADP (Burst 2) Synchronous SRAM (2.5 CYCLE READ LATENCY) OCTOBER 2014 .
The and
are synchronous, high-
performance CMOS static random access memory (SRAM)
devices.
Features
* 512Kx36 and 1Mx18 configuration available.
* On-chip Delay-Locked Loop (DLL) for wide data valid window.
* Separate independent read and write ports with concurrent read and write operations.
* Synchronous pipeline read with EARLY write operation.
* Double Data Rate (DDR) inter
Applications
* where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance
