HYB39S64800BT Datasheet (Infineon Technologies)

HYB39S64800BT, 64-MBit Synchronous DRAM

HYB 39S64400BT-7.5 Q67100-Q2781 HYB 39S64400BT-8 Q67100-Q1838 P-TSOP-54-2 (400mil) 133MHz 4B × 4M x4 SDRAM P-TSOP-54-2 (400mil) 125MHz 4B × 4M x4 SDRAM P-TSOP-54-2 (400mil) 133MHz 4B × 2M x8 SDRAM P-TSOP-54-2 (400mil) 125MHz 4B × 2M x8 SDRAM P-TSOP-54-2 (400mil) 133MHz 4B × 1M x16 SDRAM P-TSOP-54-

HYB 39S64400/800/160BT(L) 64-MBit Synchronous DRAM www.DataSheet4U.com 64-MBit Synchronous DRAM High Performance: Multiple Burst Read with Single Write Operation Units MHz ns ns ns ns Automatic and Controlled Precharge Command Data Mask for Read/Write Control (x4, x8) Data Mask for Byte Control (x16) Auto Refresh (CBR) and Self Refresh Suspend Mode and Power Down Mode 4096 Refresh Cycles / 64 ms Random Col

HYB39S64800BT Features

* CS, RAS, CAS, WE, and DQM at the positive edge of the clock. The following list shows the truth table for the operation commands.