MK2049-45 Datasheet – 3.3V Communications Clock PLL

Manufacturer: Integrated Circuit Systems

Integrated Circuit Systems

Datasheet Details

The MK2049-45 is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation.

The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input jitter.

The second PLL is a translator for frequency multiplication.

MK2049-45 3.3V Communications Clock PLL.

Packaged in 20 pin SOIC.
3.3 V + 5% operation.
Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz Locks to 8 kHz + 100 ppm (External mode) Buffer Mode allows jitter attenuation of 10 - 50 MHz input and x1 / x0.5 or x1 / x2 outputs Exact internal ratios enable zero ppm error Output rates include T1, E1,.

Brand Logo	Part Number	Description	Manufacturer
	MK2049-45	CLOCK PLL	Renesas
	MK2049-45	CLOCK PLL	Renesas

Part Number	Description
MK2049-01	Communications Clock PLL
MK2049-02	Communications Clock PLLs
MK2049-03	Communications Clock PLLs
MK2049-34	3.3 V Communications Clock PLL
MK2049-34A	3.3 Volt Communications Clock VCXO PLL
MK2049-35	3.3 V Communications Clock PLL
MK2049-36	3.3 V Communications Clock PLL
MK2042-01	Communications Clock Monitor
MK2011	Fast Ethernet Clock Source
MK2014A	Fast Ethernet Clock Source