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IDT71V546

128K x 36/ 3.3V Synchronous SRAM with ZBT Feature/ Burst Counter and Pipelined Outputs

IDT71V546 Features

* 128K x 36 memory configuration, pipelined outputs Supports high performance system speed - 133 MHz (4.2 ns Clock-to-Data Access) ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized registered outputs eliminate the need to control OE Single R/W (READ/WRITE) control pi

IDT71V546 General Description

The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAM organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turn-around. Address .

IDT71V546 Datasheet (178.20 KB)

Preview of IDT71V546 PDF

Datasheet Details

Part number:

IDT71V546

Manufacturer:

Integrated Device Technology

File Size:

178.20 KB

Description:

128k x 36/ 3.3v synchronous sram with zbt feature/ burst counter and pipelined outputs.

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IDT71V546 128K 3.3V Synchronous SRAM with ZBT Feature Burst Counter and Pipelined Outputs Integrated Device Technology

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