IDT71V546, IDT-71V Datasheet - Integrated Device Technology

IDT71V546, IDT-71V, 128K x 36/ 3.3V Synchronous SRAM with ZBT Feature/ Burst Counter and Pipelined Outputs

128K x 36, 3.3V Synchronous IDT71V546 SRAM with ZBT™

Features

* 128K x 36 memory configuration, pipelined outputs Supports high performance system speed - 133 MHz (4.2 ns Clock-to-Data Access) ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized registered outputs eliminate the need to control OE Single R/W (READ/WRITE) control pi

Applications

* 4-word burst capability (interleaved or linear) Individual byte write (BW1 - BW4) control (May tie active) Three chip enables for simple depth expansion Single 3.3V power supply (±5%) Packaged in a JEDEC standard 100-pin TQFP package clock cycle, and two cycles later its associated data cycle occurs

IDT-71V-546.pdf