* Typical tSK(o) (Output Skew) < 250ps
* ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
* VCC = 3.3V ± 0.3V, Normal Range
* VCC = 2.7V to 3.6V, Extended Range
* CMOS power levels (0.4μ W typ. static)
* All inpu
IDT74LVC16373A Datasheet (104.46 KB)
IDT74LVC16373A
Integrated Device Technology
104.46 KB
3.3v cmos 16-bit transparent d-type latch.
IDT74LVC16373A 3.3VCMOS16-BIT TRANSPARENT D-TYPE LATCH
INDUSTRIALTEMPERATURERANGE
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND.
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