CD4508BMS - CMOS Dual 4-Bit Latch
of ‘B’ Series CMOS Devices" Functional Diagram OUTPUT DISABLE D0A Q0A 4-BIT LATCH Q1A 3-STATE OUTUTS Q2A Q3A Applications * Buffer Storage * Holding Registers * Data Storage and Multiplexing D1A D2A D3A STROBE RESET OUTPUT DISABLE D0B D1B D2B D3B STROBE RESET Description
CD4508BMS Features
* High-Voltage Types (20-Volt Rating)
* Two Independent 4-Bit Latches
* Individual Master Reset for Each 4-Bit Latch
* 3-State Outputs with High-Impedance State for Bus Line Applications
* Medium-Speed Operation: tPHL = tPLH = 70nS (Typ.) at VDD = 10V and CL =
