* Pixel Clock Frequencies up to 250MHz
* Very Low Jitter
* Digital Phase Adjustment (DPA) for Clock Outputs
* Balanced PECL Differential Outputs
* Single-Ended SSTL_3 Clock Outputs
* Double-Buffered PLL/DPA Control Registers
* Independent Softw
HI5634
Intersil Corporation
160.77 KB
High performance programmable phase-locked loop.
HI5634
PRELIMINARY
Data Sheet
May 1999
File Number
4745
High Performance Programmable Phase-Locked Loop for LCD Applications
The HI5634 is a low .
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