LMA2009JC20 Datasheet - LOGIC Devices Incorporated

LMA2009JC20 12 x 12-bit Multiplier-Accumulator

Data present at the A and B input registers is latched on the rising edges of CLK A and CLK B respectively. RND, TC, ACC, and SUB controls are latched on the rising edge of the logical OR of CLK A and CLK B. TC specifies the input as two’s complement (TC HIGH) or unsigned magnitude (TC LOW). RND, wh.

LMA2009JC20 Features

* u 20 ns Multiply-Accumulate Time u Low Power CMOS Technology u Replaces Fairchild TDC1009/ TMC2009 u Two’s Complement or Unsigned Operands u Accumulator Performs Preload, Accumulate, and Subtract u Three-State Outputs u 68-pin PLCC, J-Lead LMA1009/2009 BLOCK DIAGRAM CLK A CLK B TC ACC SUB REGIST

LMA2009JC20_LOGICDevicesIncorporated.pdf