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MAX3674 Network Clock Synthesizer

MAX3674 Description

19-2483; Rev 0; 12/07 High-Performance, Dual-Output, Network Clock Synthesizer www.datasheet4u.com General .
Features. 21. Two Differential LVPECL-Compatible Outputs. Cycl.

MAX3674 Features

* 21.25MHz to 1360MHz Programmable PLL Synthesized Output Clocks
* Two Differential LVPECL-Compatible Outputs
* Cycle-to-Cycle Jitter 1.6ps RMS and Period Jitter 0.9ps RMS at 500MHz
* On-Chip Crystal Oscillator or Selectable LVCMOS-Compatible Reference Clock Input

MAX3674 Applications

* It integrates a crystal oscillator, a lownoise phase-locked loop (PLL), programmable dividers, and high-frequency LVPECL output buffers. The PLL generates a high-frequency clock based on a low-frequency reference clock provided by the on-chip crystal oscillator or an external LVCMOS clock. The MAX3

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Network Clock Synthesizer Maxim Integrated Products
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