ZL40260 Datasheet - Microsemi

ZL40260, Low Additive Jitter 2 x10 LVPECL Fanout Buffer

Data Sheet ZL40260 Low Skew, Low Additive Jitter 2 x10 LVPECL Fanout Buffer .
6 Functional Description 8 Clock Inputs 8 Clock Outputs 11 Termination of unused inputs and outputs 13 Power Consumption 13 Power Supply Filtering.

Features

* Two inputs accept any differential (LVPECL, HCSL, LVDS, SSTL, CML) or single ended LVCMOS signal
* Ten 2.5V/3.3V LVPECL outputs
* Ultra-low additive jitter: 53fs for 125 MHz clock measured in 12KHz to 20MHz band
* Supports clock frequencies from 0 to 1.6GHz
* Supports 2.5V or 3

Applications

* General purpose clock distribution
* Low jitter clock trees
* Logic translation
* Clock and data signal restoration
* Wired communications: OTN, SONET/SDH, GE, 10 GE, FC and 10G FC
* PCI Express generation 1/2/3/4 clock distribution
* Wireless communications
* High

ZL40260-Microsemi.pdf