MT8941 Datasheet (Mitel Networks Corporation) - CMOS ST-BUS FAMILY Advanced T1/CEPT Digital Trunk PLL

MT8941, CMOS ST-BUS FAMILY Advanced T1/CEPT Digital Trunk PLL

The MT8941 is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS.

The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz.

The timing signals for the CEPT transmission link and

MT8941 Features

* Provides T1 clock at 1.544 MHz locked to an 8 kHz reference clock (frame pulse) Provides CEPT clock at 2.048 MHz and STBUS clock and timing signals locked to an internal or external 8 kHz reference clock Typical inherent output jitter (unfiltered)= 0.07 UI peak-to-peak Typical ji