M2S28D20ATP-75 Datasheet, Dram, Mitsubishi

✔ M2S28D20ATP-75 Features

- Vdd=Vddq=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differenti

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M2S28D20ATP-75

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Mitsubishi

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1.19 MB

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📄 Datasheet

Description:

128m double data rate synchronous dram. M2S28D20ATP is a 4-bank x 8388608-word x 4-bit, M2S28D30ATP is a 4-bank x 4194304-word x 8-bit, M2S28D40ATP is a 4-bank x 2097152-wor

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M2S28D20ATP-75 128M Double Data Rate Synchronous DRAM Mitsubishi