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M2S28D30ATP

128M Double Data Rate Synchronous DRAM

M2S28D30ATP Features

* - Vdd=Vddq=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each po

M2S28D30ATP General Description

M2S28D20ATP is a 4-bank x 8388608-word x 4-bit, M2S28D30ATP is a 4-bank x 4194304-word x 8-bit, M2S28D40ATP is a 4-bank x 2097152-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registere.

M2S28D30ATP Datasheet (1.19 MB)

Preview of M2S28D30ATP PDF

Datasheet Details

Part number:

M2S28D30ATP

Manufacturer:

Mitsubishi

File Size:

1.19 MB

Description:

128m double data rate synchronous dram.
DDR SDRAM (Rev.0.1) Jun,'00 Preliminary MITSUBISHI LSIs M2S28D20/ 30/ 40ATP 128M Double Data Rate Synchronous DRAM PRELIMINARY Some of contents are.

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M2S28D40ATP - 128M Double Data Rate Synchronous DRAM (Mitsubishi)
DDR SDRAM (Rev.0.1) Jun,'00 Preliminary MITSUBISHI LSIs M2S28D20/ 30/ 40ATP 128M Double Data Rate Synchronous DRAM PRELIMINARY Some of contents are.

M2S28D40ATP-10 - 128M Double Data Rate Synchronous DRAM (Mitsubishi)
DDR SDRAM (Rev.0.1) Jun,'00 Preliminary MITSUBISHI LSIs M2S28D20/ 30/ 40ATP 128M Double Data Rate Synchronous DRAM PRELIMINARY Some of contents are.

M2S28D40ATP-75 - 128M Double Data Rate Synchronous DRAM (Mitsubishi)
DDR SDRAM (Rev.0.1) Jun,'00 Preliminary MITSUBISHI LSIs M2S28D20/ 30/ 40ATP 128M Double Data Rate Synchronous DRAM PRELIMINARY Some of contents are.

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M2S28D30ATP 128M Double Data Rate Synchronous DRAM Mitsubishi

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