M2S28D40ATP, M2S - 128M Double Data Rate Synchronous DRAM

Mitsubishi

The M2S28D40ATP by Mitsubishi is a 128M Double Data Rate Synchronous DRAM. Below is the official datasheet preview.

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M2S28D40ATP 128M Double Data Rate Synchronous DRAM by Mitsubishi - Datasheet Preview — Official preview page of the **M2S28D40ATP** 128M Double Data Rate Synchronous DRAM datasheet (Mitsubishi).

Datasheet Details

Part number	M2S28D40ATP, M2S
Manufacturer	Mitsubishi
File Size	1.19 MB
Description	128M Double Data Rate Synchronous DRAM
Datasheet	M2S-28D.pdf
Note	This datasheet PDF includes multiple part numbers: M2S28D40ATP, M2S. Please refer to the document for exact specifications by model.
Additional preview pages of the M2S28D40ATP datasheet.

M2S28D40ATP Product details

Description

M2S28D20ATP is a 4-bank x 8388608-word x 4-bit, M2S28D30ATP is a 4-bank x 4194304-word x 8-bit, M2S28D40ATP is a 4-bank x 2097152-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface.

Features

- Vdd=Vddq=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge; - data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2.0/2.5 (programmable) - Burst length- 2/4/8 (programmabl.

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Other Datasheets by Mitsubishi

M2S28D40ATP-10 - 128M Double Data Rate Synchronous DRAM
M2S28D40ATP-75 - 128M Double Data Rate Synchronous DRAM
M2S28D20ATP - 128M Double Data Rate Synchronous DRAM
M2S28D20ATP-10 - 128M Double Data Rate Synchronous DRAM
M2S28D20ATP-75 - 128M Double Data Rate Synchronous DRAM
M2S28D30ATP - 128M Double Data Rate Synchronous DRAM

Published: May 2, 2005 |