Datasheet4U Logo Datasheet4U.com

M2S56D30ATP-75A Datasheet - Mitsubishi

M2S56D30ATP-75A 256M Double Data Rate Synchronous DRAM

M2S56D20ATP / AKT is a 4-bank x 16777216-word x 4-bit, M2S56D30ATP / AKT is a 4-bank x 8388608-word x 8-bit, M2S56D40ATP/ AKT is a 4-bank x 4194304-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK.Input .

M2S56D30ATP-75A Features

* - VDD=VDDQ=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions - Commands are entered on each positive CLK edge - Data and dat

M2S56D30ATP-75A Datasheet (768.53 KB)

Preview of M2S56D30ATP-75A PDF

Datasheet Details

Part number:

M2S56D30ATP-75A

Manufacturer:

Mitsubishi

File Size:

768.53 KB

Description:

256m double data rate synchronous dram.

📁 Related Datasheet

M2S56D30ATP-75 256M Double Data Rate Synchronous DRAM (Mitsubishi)

M2S56D30ATP-75AL 256M Double Data Rate Synchronous DRAM (Mitsubishi)

M2S56D30ATP-75L 256M Double Data Rate Synchronous DRAM (Mitsubishi)

M2S56D30ATP-10 256M Double Data Rate Synchronous DRAM (Mitsubishi)

M2S56D30ATP-10L 256M Double Data Rate Synchronous DRAM (Mitsubishi)

M2S56D30ATP 256M Double Data Rate Synchronous DRAM (Mitsubishi)

M2S56D30ATP75A 256M Double Data Rate Synchronous DRAM (Mitsubishi)

M2S56D30AKT 256M Double Data Rate Synchronous DRAM (Mitsubishi)

M2S56D30AKT-10 256M Double Data Rate Synchronous DRAM (Mitsubishi)

M2S56D30AKT-10L 256M Double Data Rate Synchronous DRAM (Mitsubishi)

TAGS

M2S56D30ATP-75A 256M Double Data Rate Synchronous DRAM Mitsubishi

Image Gallery

M2S56D30ATP-75A Datasheet Preview Page 2 M2S56D30ATP-75A Datasheet Preview Page 3

M2S56D30ATP-75A Distributor