MC88915FN55 Low Skew CMOS PLL Clock Driver

Motorola

MC88915FN55 Description

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Skew CMOS PLL Clock Driver The MC88915 Clock Driver utilizes phase *locked loop technology to lock .
on page 11). state phase and frequency lock.

MC88915FN55 Features

* Five Outputs (QO
* Q4) with Output
* Output Skew < 500 ps each being phase and frequency locked to the SYNC input
* The phase variation from part
* to
* part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the tPD specification, which

MC88915FN55 Applications

* when a central system clock must be distributed synchronously to multiple boards (see Figure 7). Five “Q” outputs (QO
* Q4) are provided with less than 500 ps skew between their rising edges. The Q5 output is inverted (180° phase shift) from the “Q” outputs. The 2X_Q output runs at twice the “

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Datasheet Details

Part number: MC88915FN55
Manufacturer: Motorola
File Size: 147.04 KB
Datasheet: MC88915FN55_MotorolaInc.pdf
Description: Low Skew CMOS PLL Clock Driver

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Low Skew CMOS PLL Clock Driver Motorola

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