MC88915FN55PLCC Datasheet - Motorola

MC88915FN55PLCC Low Skew CMOS PLL Clock Driver

on page 11). A lock indicator output (LOCK) will go high when the loop is in steady *state phase and frequency lock. The LOCK output will go low if phase *lock is lost or when the PLL_EN pin is low. Under certain conditions the lock output may remain low, even though the part is phase<.

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Skew CMOS PLL Clock Driver The MC88915 Clock Driver utilizes phase locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for high performance PC’s and workstations. The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple components on a board. The PLL also allows the.

MC88915FN55PLCC Features

* Five Outputs (QO

* Q4) with Output

* Output Skew < 500 ps each being phase and frequency locked to the SYNC input

* The phase variation from part

* to

* part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the tPD specification, which

MC88915FN55PLCC Datasheet (147.04 KB)