MCM69P536C Datasheet (Motorola) - 32K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM

MCM69P536C, 32K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM

Pin Locations 85 84 Symbol ADSC ADSP Type Input Input Description Synchronous Address Status Controller: Initiates READ, WRITE, or chip deselect cycle.

Synchronous Address Status Processor: Initiates READ, WRITE, or chip deselect cycle (exception * chip deselect does not occur when ADSP is

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM69P536C/D 32K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM The MCM69P536C is a 1M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPC™, 486, i960™, and Pentium™ microprocessors.

It is organized as 32K words of 36 bits each.

This device integrates input registers, an output register, a 2 bit address counter, and high speed SRAM on

MCM69P536C Features

* r Dissipation (See Note 2) Temperature Under Bias Storage Temperature Symbol VDD Vin, Vout Iout PD Tbias Tstg Value

* 0.5 to + 4.6

* 0.5 to 6.0 ± 20 1.6

* 10 to 85

* 55 to 125 Unit V V mA W °C °C This device contains circuitry to protect the inputs against damage due