MCM69P618C Datasheet - Motorola

MCM69P618C 64K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM

Pin Locations 85 84 Symbol ADSC ADSP Type Input Input Description Synchronous Address Status Controller: Initiates READ, WRITE, or chip deselect cycle. Synchronous Address Status Processor: Initiates READ, WRITE, or chip deselect cycle (exception * chip deselect does not occur when ADSP is .

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM69P618C/D 64K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM The MCM69P618C is a 1M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPC™, 486, i960™, and Pentium™ microprocessors. It is organized as 64K words of 18 bits each. This device integrates input registers, an output register, a 2 bit address counter, and high speed SRAM on.

MCM69P618C Features

* to + 4.6

* 0.5 to 6.0 ± 20 1.6

* 10 to 85

* 55 to 125 Unit V V mA W °C °C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any vo

MCM69P618C Datasheet (205.04 KB)

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Datasheet Details

Part number:

MCM69P618C

Manufacturer:

Motorola

File Size:

205.04 KB

Description:

64k x 18 bit pipelined burstram synchronous fast static ram.

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MCM69P618C 64K Bit Pipelined BurstRAM Synchronous Fast Static RAM Motorola

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